1. Technical Field
The present invention relates to a compiler, particularly to the Just In Time Compiler of Java (a trademark of Sun Microsystems).
2. Prior Art
Currently, Java is considered not merely as a common language for network computing but also as a standard object-oriented language independent of platforms. While Java is more descriptive than other languages, there is still a problem in execution speed.
In a Java program, execution of a thread, which is a unit for executing a program, has a characteristic that it may be synchronously or asynchronously interrupted by an exception. Any execution interrupted by an exception must generally re-start from a code in Java""s catch or finally block which can handle the exception. A synchronous exception in this case is one which is issued as a result of object handling or by means of explicit description. On the other hand, an asynchronous exception is one which is issued from one thread to another thread, asynchronously.
The timing of occurrence of such exceptions is defined in xe2x80x9cThe Java Language Specification 11.3.1xe2x80x9d (James Goslimg, Bill Joy, Guy Steele, ADDISON-WESLEY ISBN 0-201-63451-1, 1996). That is, in a program, any execution statement before an exception occurred must be executed and any execution statement after the exception occurred must not be executed. These are called precise exceptions. Because of this language specification, and because almost all instructions which refer to an object (memory) may cause an exception, any change of an order of executing instructions or referring to memory and any reduction of referring to memory by using a register were significantly restricted when compiling a Java program.
On the other hand, in the languages which do not have precise exceptions defined such as FORTRAN and C, there is no restriction as to an order of executing instructions, an order of referring to memory, and reduction of memory reference, as far as maintaining a data dependance relationship. These allow utilization of data in a register or data cache or utilization of CPU resources to be improved to acquire maximum system performance. Thus, optimization technique for acquiring maximum hardware performance has a narrower scope for Java or cannot be applied to Java, so an application written in Java often has lower execution speed than ones written in FORTRAN or C.
As regards an asynchronous exception, a technique proposed for optimizing to a degree while assuring a precise exception is polling (The Java Language Specification 11.3.2). Generally, even if an order of executing instructions is changed in a section of a program, it looks externally as if a precise exception is assured when an exception is handled after executing all the instructions to be executed originally before the instruction to which the exception has occurred (The Java Language Specification 11.3.1). In this technique of polling, a thread itself examines whether an exception has occurred and handles the exception if there is one.
As regards polling, however, overhead becomes a big problem since it is checked whether or not there is an exception even when no exception has occurred. As re-ordering of instructions for optimization is frequently performed, the overhead trades off with optimization. Consequently, since exception handling is relatively costly, it cannot be optimized and performance of a CPU with high throughput cannot be well used.
As another method of exception handling without overhead of exception check such as polling, there is interrupt processing. In interrupt processing, an exception related to a thread is handled by an interrupt handler of the thread. For instance, if thread T has an exception synchronously or asynchronously, the interrupt handler is activated in a context of thread T to handle the exception. A context of a thread is the entire contents of registers essential for executing the thread, including a program counter and a stack pointer. If execution of a thread is suspended, the context is retained for next restart of the execution.
Here is a point to pay attention to. A Java program must be continuously executed for the following two reasons, even after an exception has occurred. Even when a thread has an exception, it cannot immediately stop execution. The first reason is that if a program is in the scope of exception handling described in Java""s try at the occurrence of the exception, the program must restart the execution from a program clause described with catch or finally which is usually able to handle the exception. The second reason is that, as aforementioned, if an order of executing instructions is changed in section A-B and an exception has occurred in the section, exception handling must be started after having executed the entire section A-B in order to assure the precise exception.
As regards the interrupt processing considered so far, an instruction to be executed in a case indicated in the above second reason is not executed since exception handling is started immediately after an exception has occurred. Thus, there is a problem to which the precise exception cannot be assured by an optimization code. An object of the present invention is to handle exceptions quickly by means of interrupt processing while assuring the precise exception.
It is also an object to enable instructions to be re-ordered while assuring the precise exception.
It is additional object to provide a compiler which enables high speed execution while assuring the precise exception.
A compiler in the present invention performs the following process. Namely, it executes the steps of: re-ordering an instruction included in a program; and if a first instruction which has an affect, which is observable from the outside at the execution, or a second instruction which may cause an exception is moved so as to be executed before an instruction to be executed before the first or the second instruction in the original order, registering a section as an interrupt inhibited section, wherein the section is from the first or the second instruction position after the movement to a predetermined instruction position before the former position of the first or the second instruction. This registration is performed to the program, and more specifically, to each routine (method) of the program. Thus, when an exception occurs, information becomes easily obtainable as to whether or not it is a section which requires a process to assure the precise exception.
Moreover, it is also possible, if a part of an interrupt inhibited section A overlaps another interrupt inhibited section B including an instruction to be executed after instructions included in the interrupt inhibited section A, to execute a step of registering an instruction within the interrupt inhibited section A, which is made invalid if an exception occurs within the interrupt inhibited section A. This is a process for xe2x80x9cadding a sectionxe2x80x9d in the embodiment. If the instruction to be made invalid is executed, the precise exception cannot be assured.
In addition, if an interrupt inhibited section includes another interrupt inhibited section, a step of integrating another interrupt inhibited section may further be executed. This has an effect of decreasing the sections to be registered.
Also, if two interrupt inhibited sections related to the first instruction partly overlap, a step of registering the section covered by the two interrupt inhibited sections as an interrupt inhibited section may further be executed. When there are too many sections, they are integrated and the number of sections is reduced in this way.
Moreover, the above step of registering may also comprise the steps of: generating an interrupt inhibited sections map by arranging registered interrupt inhibited sections by each routine of the program; and generating a code for registering in the routine the interrupt inhibited sections map and an interrupt handler which uses the interrupt inhibited sections map.
Meanwhile, a rear end of an interrupt inhibited section is decided by the xe2x80x9cpredetermined instructionxe2x80x9d, but it may also be an instruction immediately preceding the first or the second instruction position before the movement, which has an affect observable from the outside at the execution. Or, it may also simply be an instruction preceding by one position the first or the second instruction before the movement.
On the other hand, processing in the event that an exception has occurred is as follows. Namely, following steps are executed: issuing an interrupt in response to an occurrence of the exception; determining whether or not, from a state of a processing interrupted by the interrupt, an instruction at the interrupt is an instruction among the interrupt inhibited section associated with the interrupted processing; if the instruction at the interrupt is an instruction among the interrupt inhibited section associated with the interrupted processing, generating a branch instruction to a code for handling the exception after the interrupt inhibited section; and restarting the execution of instructions following the instruction at the interrupt. Thus, it is possible to easily determine whether it is a case where an exception is ordinarily processed or a case where processing of the present invention is required, and to branch into an exception handling code after executing instructions for assuring the precise exception.
It is also possible that the generating step-comprises the steps of copying codes among the interrupt inhibited section to another area; and generating a branch code to the code for handling an exception after the copied codes. As a special process is executed, it may have less effect on other processes to execute codes by copying them among the interrupt inhibited section to another area.
Furthermore, the generating step comprises a step of, if there exists an instruction invalid at an exception among the interrupt inhibited section, setting so as not to execute the instruction invalid at an exception. This is for assuring the precise exception.
It is also possible that the determining step comprises the steps of: if an exception occurs during execution of a second instruction, determining as to an interrupt inhibited section registered in relation to the second instruction; and if an interrupt is issued by any other processing, determining as to an interrupt inhibited section registered in relation to the first instruction. This is intended to have each interrupt inhibited section include information of whether an exception is synchronous or asynchronous, and to change the interrupt inhibited section to be used for the determining step depending on how the exception occurred.
It is also possible to further comprise a step of, if an exception occurs as to the second instruction during execution of the instruction among the interrupt inhibited section, branching into a routine for handling the exception. In addition, the instruction invalid at an exception may be a first instruction which has an affect, which is observable from the outside at the execution, or a second instruction which may cause an exception, which may cause a problem in assuring the precise exception.
As above, the present invention has been explained as a processing flow. However, it is also possible to implement a computer which executes such processing or to implement it as a program for executing such processing.
Moreover, a program for performing such processing may be stored on storage media such as an MO disk, a floppy disk or a CD-ROM.